Designing a Full Adder

We begin with truth tables for the sum and carry-out bits produced when two binary numbers are added together with a carry-in. First we will look at the sum expression. given two input bits and a carry-in, we have three variables and need a truth table with eight rows to represent all possible combinations of three binary variables.

After adding all combinations we see that the sum should be 1 whenever the combination of inputs is odd. This is an odd function, which could easily be represented by exclusive-or gates. But or goal here is to practice with truth tables, disjunctive normal form, karnaugh maps and designing digital circuits. So we begin by developing the disjunctive normal form for the following truth table representing the sum:

Binary One-bit Full Adder Sum Table
x	y	Cin	Sum
0	0	0	0
0	0	1	1	x’y’Cin
0	1	0	1	x’yCin’
0	1	1	0
1	0	0	1	xy’Cin’
1	0	1	0
1	1	0	0
1	1	1	1	xyCin

Sum = x’y’Cin + x’yCin’ + xy’Cin’ + xyCin.

Now that we have determined the sum-of-products (disjunctive normal form) for the sum expression, we attempt to reduce this to a simpler expression requiring fewer gates to build. Here we will use the karnaugh map:

x \ y Cin	0 0	0 1	1 1	1 0
0	0	1	0	1
1	1	0	1	0

No simplification up to this point. So we move on to the carry-out expression.

The carry-out truth table represents a majority circuit, the output is high whenever the number of high inputs is greater than the number of low inputs. Again we determine the disjunctive normal form for the Cout expression:

Binary One-bit Full Adder Cout Table
x	y	Cin	Cout
0	0	0	0
0	0	1	0
0	1	0	0
0	1	1	1	x’yCin
1	0	0	0
1	0	1	1	xy’Cin
1	1	0	1	xyCin’
1	1	1	1	xyCin

Cout = x’yCin + xy’Cin + xyCin’ + xyCin.
Using the karnaugh map we get:

x \ y Cin	0 0	0 1	1 1	1 0
0	0	0	1	0
1	0	1	1	1

We can make three blocks of two to get a reduced circuit:

Cout = xCin + xy + yCin.
We should take a moment to verify that this is indeed an equivalent circuit by ensuring that the truth table is the same for both.

x	y	Cin	xCin + xy + yCin
0	0	0	0	0	0	0
0	0	1	0	0	0	0
0	1	0	0	0	0	0
0	1	1	0	0	1	1
1	0	0	0	0	0	0
1	0	1	1	0	0	1
1	1	0	0	1	0	1
1	1	1	1	1	1	1

So this reduced circuit is the same. We combine the results into a single circuit with three inputs and two outputs to get the following drawing:

ICs used for the Full Adder

SN7404 Hex Not GATE

SN7411 Hex Not GATE

SN74HC4072 4-Input OR Gate